Integrated circuits (ICs) generally and particularly those employing metal-oxide-semiconductor (MOS) type field-effect transistors (FETs) are susceptible to damage during handling from the discharge of static electricity (electrostatic discharge). To protect a metal-oxide-semiconductor-type integrated circuit from damage from electrostatic discharge (ESD), common practice is to connect the input and/or output pads of the integrated circuit each to an associated (internal) electrostatic-discharge-protection device (circuit).
Ideally, an electrostatic-discharge-protection device (circuit) 1) should not leak charge, 2) should not capacitively load the associated pad (by more than one picofarad), and 3) should, responsive to an electrostatic-discharge pulse, clamp the level of the voltage developed between the pad and circuit ground to a voltage level (less than 15 volts) low enough to protect devices connected to the pad while discharging the static charge. Further, ideally, an electrostatic-discharge-protection circuit 4) should conduct the an electrostatic discharge in a uniform flow. A uniform charge flow minimizes the required size of the electrostatic-discharge-protection device and minimizes local heating of the device which can cause secondary breakdown, locally damaging the device.
Typical of prior-art-type electrostatic-discharge-protection devices (circuits) is the device (transistor) which is illustrated in FIG. 1 of the drawing generally designated by the number 110. Device 110 is configured as a gated diode with the device gate, well, and source connected to circuit ground and with the device drain connected to the associated (input or output) pad, which is designated in the drawing by the number 120. When so configured, device 110 functions as illustrated in FIG. 2. Specifically, device 110 (shown in FIG. 1) functions as the combination of a gate grounded N-channel-type metal-oxide-semiconductor (N-MOS) transistor (designated 210 in FIG. 2) connected in parallel with a base-grounded lateral NPN bipolar transistor (designated 212 in FIG. 2).
Fortunately, device (circuit) 110 (shown in FIG. 1) is particularly useful in protecting the associated integrated circuit from negative electrostatic-discharge pulses (pulses of the type in which the associated pad is driven to a negative potential with respect to circuit ground). Specifically, responsive to a negative electrostatic-discharge pulse, both the N-channel transistor (designated 210 in FIG. 2) and the bipolar transistor (designated 212 in FIG. 2) are turned on. The transistors conduct a uniform level of current and develop a low voltage drop across the device (gated diode).
Unfortunately, device (circuit) 110 (shown in FIG. 1) is not particularly useful in protecting the associated integrated circuit from positive electrostatic-discharge pulses (pulses of the type in which the associated pad is driven to a positive potential with respect to circuit ground). Specifically, responsive to a positive electrostatic-discharge pulse, the gated diode (device 110) breaks down with a non-uniform charge flow and develops across the diode (device 110) a relatively high voltage drop.
In the U.S. Pat. No. 3,746,946 of Lowell Clark and the U.S. Pat. No. 3,777,216 of William Armstrong, to protect a (first) insulated gate field effect transistor, a second insulated gate field effect transistor is included, configured with the transistor channel connected between the gate of the first transistor and circuit ground. In the U.S. Pat. No. 3,746,946 of Lowell Clark, the gate of the second transistor is connected to a power supply potential (Vdd). In the U.S. Pat. No. 3,777,216 of William Armstrong, the gate of the second transistor is connected to the anode of a diode, the cathode of which is connected to circuit ground.